Según la pregunta vinculada, la solución más simple es hacer **que el procesador clásico realice tales operaciones si es posible** . Por supuesto, eso puede no ser posible, por lo que queremos crear un *sumador* .

Hay dos tipos de sumadores de un solo bit: el *sumador* y el *sumador completo* . El medio sumador toma las entradas y B y emite la 'suma' (operación XOR) S = A ⊕ B y el 'carry' (operación Y) C = A ⋅ B . Un sumador completo también tiene la 'acarreo en' C i n de entrada y el 'llevar a cabo' de salida C o u t , sustituyendo C . Esto devuelve S = A C o u t = CUNA$A$si$B$S= A ⊕ B$S=A\oplus B$do= A ⋅ B$C=A\cdot B$doyo n${C}_{in}$doo u t${C}_{out}$do$C$S= A ⊕ B ⊕ Cyo n$S=A\oplus B\oplus {C}_{in}$ y .doo u t= Cyo n⋅ ( A + B ) + A ⋅ B${\mathrm{do}}_{o\mathrm{tu}t}={\mathrm{do}}_{\mathrm{yo}\mathrm{norte}}\cdot (\mathrm{UNA}+\mathrm{si})+\mathrm{UNA}\cdot \mathrm{si}$

## Versión cuántica del medio sumador

Mirando la puerta CNOT en el registro de qubit registro de control B : CNOT A → B | 0 ⟩ A | 0 ⟩ BUNA$\mathrm{UNA}$si$\mathrm{si}$

CNOTA→B|0⟩A|0⟩BCNOTA→B|0⟩A|1⟩BCNOTA→B|1⟩A|0⟩BCNOTA→B|1⟩A|1⟩B=|0⟩A|0⟩B=|0⟩A|1⟩B=|1⟩A|1⟩B=|1⟩A|0⟩B,$$\begin{array}{rl}{\text{CNOT}}_{A\to B}{|0\u27e9}_{A}{|0\u27e9}_{B}& ={|0\u27e9}_{A}{|0\u27e9}_{B}\\ {\text{CNOT}}_{A\to B}{|0\u27e9}_{A}{|1\u27e9}_{B}& ={|0\u27e9}_{A}{|1\u27e9}_{B}\\ {\text{CNOT}}_{A\to B}{|1\u27e9}_{A}{|0\u27e9}_{B}& ={|1\u27e9}_{A}{|1\u27e9}_{B}\\ {\text{CNOT}}_{A\to B}{|1\u27e9}_{A}{|1\u27e9}_{B}& ={|1\u27e9}_{A}{|0\u27e9}_{B},\end{array}$$

which immediately gives the output of the

B$B$ register as

A⊕B=S$A\oplus B=S$. However, we have yet to compute the carry and the state of the

B$B$ register has changed so we also need to perform the AND operation. This can be done using the 3-qubit Toffoli (controlled-CNOT/CCNOT) gate. This can be done using registers

A$A$ and

B$B$ as control registers and initialising the third register

(C)$\left(C\right)$ in state

|0⟩$|0\u27e9$, giving the output of the third register as

A⋅B=C$A\cdot B=C$. Implementing Toffoli on registers

A$A$ and

B$B$ controlling register

C$C$ followed by CNOT with

A$A$ controlling

B$B$ gives the output of register

B$B$ as the sum and the output of register

C$C$ as the carry. A quantum circuit diagram of the half-adder is shown in figure 1.

Figure 1: Circuit Diagram of a half-adder, consisting of Toffoli followed by CNOT. Input bits are A$A$ and B$B$, giving the sum S$S$ with carry out C$C$.

## Quantum version of the full adder

Shown in figure 2, a simple way of doing this for single bits is by using 4$4$ qubit registers, here labelled A$A$, B$B$, Cin${C}_{in}$ and 1$1$, where 1$1$ starts in state |0⟩$|0\u27e9$, so the initial state is |A⟩|B⟩|Cin⟩|0⟩$|A\u27e9|B\u27e9|{C}_{in}\u27e9|0\u27e9$:

- Apply Toffoli using A$A$ and B$B$ to control 1$1$: |A⟩|B⟩|Cin⟩|A⋅B⟩$|A\u27e9|B\u27e9|{C}_{in}\u27e9|A\cdot B\u27e9$
- CNOT with A$A$ controlling B$B$: |A⟩|A⊕B⟩|Cin⟩|A⋅B⟩$|A\u27e9|A\oplus B\u27e9|{C}_{in}\u27e9|A\cdot B\u27e9$
- Toffoli with B$B$ and Cin${C}_{in}$ controlling 1$1$: |A⟩|A⊕B⟩|Cin⟩|A⋅B⊕(A⊕B)⋅Cin=Cout⟩$|A\u27e9|A\oplus B\u27e9|{C}_{in}\u27e9|A\cdot B\oplus (A\oplus B)\cdot {C}_{in}={C}_{out}\u27e9$
- CNOT with B$B$ controlling Cin${C}_{in}$: |A⟩|A⊕B⟩|A⊕B⊕Cin=S⟩|Cout⟩$|A\u27e9|A\oplus B\u27e9|A\oplus B\oplus {C}_{in}=S\u27e9|{C}_{out}\u27e9$

A final step to get back the inputs A$A$ and B$B$ is to apply a CNOT with register A$A$ controlling register B$B$, giving the final output state as

|ψout⟩=|A⟩|B⟩|S⟩|Cout⟩$$|{\psi}_{out}\u27e9=|A\u27e9|B\u27e9|S\u27e9|{C}_{out}\u27e9$$

This gives the output of register Cin${C}_{in}$ as the sum and the output of register 2$2$ as carry out.

Figure 2: Circuit diagram of a full adder. Input bits are A$A$ and B$B$ along with a carry in Cin${C}_{in}$, giving the sum S$S$ with carry out Cout${C}_{out}$.

## Quantum version of the ripple carry adder

A simple extension of the full adder is a ripple carry adder, named as it 'ripples' the carry out to become the carry in of the next adder in a series of adders, allowing for arbitrarily-sized (if slow) sums. A quantum version of such an adder can be found e.g. here

## Actual implementation of a half-adder

For many systems, implementing a Toffoli gate is far from as simple as implementing a single qubit (or even two qubit) gate. This answer gives a way of decomposing Toffoli into multiple smaller gates. However, in real systems, such as IBMQX, there can also be issues on which qubits can be used as targets. As such, a real life implementation on IBMQX2 looks like this:

Figure 3: Implementation of a half-adder on IBMQX2. In addition to decomposing the Toffoli gate into multiple smaller gates, additional gates are required as not all qubit registers can be used as targets. Registers q[0] and q[1] are added to get the sum in q[1] and the carry in q[2]. In this case, the result q[2]q[1] should be 10. Running this on the processor gave the correct result with a probability of 42.8% (although it was still the most likely outcome).